16#ifndef HIGHWAY_HWY_CACHE_CONTROL_H_
17#define HIGHWAY_HWY_CACHE_CONTROL_H_
23#if !defined(__SSE2__) || (HWY_COMPILER_CLANG && HWY_ARCH_X86_32)
24#undef HWY_DISABLE_CACHE_CONTROL
25#define HWY_DISABLE_CACHE_CONTROL
28#ifndef HWY_DISABLE_CACHE_CONTROL
30#if HWY_ARCH_X86 && !HWY_COMPILER_MSVC
41#define HWY_STREAM_MULTIPLE 16
44#if HWY_ARCH_X86 && !defined(HWY_DISABLE_CACHE_CONTROL) && !HWY_COMPILER_MSVC
45#define HWY_ATTR_CACHE __attribute__((target("sse2")))
53#pragma push_macro("LoadFence")
61#if HWY_ARCH_X86 && !defined(HWY_DISABLE_CACHE_CONTROL)
67#pragma pop_macro("LoadFence")
74#if HWY_ARCH_X86 && !defined(HWY_DISABLE_CACHE_CONTROL)
84#ifndef HWY_DISABLE_CACHE_CONTROL
86 _mm_prefetch(
reinterpret_cast<const char*
>(p), _MM_HINT_T0);
90 __builtin_prefetch(p, 0, 3);
97#if HWY_ARCH_X86 && !defined(HWY_DISABLE_CACHE_CONTROL)
109#ifndef HWY_DISABLE_CACHE_CONTROL
112#elif HWY_ARCH_ARM_A64 && HWY_COMPILER_CLANG
116#elif HWY_ARCH_ARM && HWY_COMPILER_GCC
117 __asm__
volatile(
"yield" :::
"memory");
118#elif HWY_ARCH_PPC && HWY_COMPILER_GCC
119 __asm__
volatile(
"or 27,27,27" :::
"memory");
#define HWY_INLINE
Definition base.h:101
#define HWY_ATTR_CACHE
Definition cache_control.h:47
HWY_INLINE HWY_ATTR_CACHE void FlushStream()
Definition cache_control.h:73
HWY_INLINE HWY_ATTR_CACHE void Prefetch(const T *p)
Definition cache_control.h:82
HWY_INLINE HWY_ATTR_CACHE void Pause()
Definition cache_control.h:108
HWY_INLINE HWY_ATTR_CACHE void LoadFence()
Definition cache_control.h:60
HWY_INLINE HWY_ATTR_CACHE void FlushCacheline(const void *p)
Definition cache_control.h:96